In any back-end, integrated circuit (IC) development process, it is desirable to ensure that the hardware works correctly in the expected operating space before the IC is shipped in volume. The challenge is to do a thorough job so that ICs are not deployed in the field, and then significant problems are subsequently discovered (e.g., by an original equipment manufacturer (OEM)). However, this is not always possible. One reason is that insufficient time may be available for cycling the hardware through every possible state and situation. Another reason is that certain aspects of the hardware and state machine functionality are opaque (i.e., not observable).
Some prior systems implemented extremely targeted hardware elements buried deep within a processor core to pipe out functional signatures that characterize occurrences within the core, thus making certain aspects of core functioning externally visible outside a chip. However, when dense content is executed (e.g., by shortening up test vectors), the effects of certain failures may never become visible at the pin boundary of the chip unless execution is continued for a sufficiently long period of time. Accordingly, such failures may remain undetected.